1. Field of the Invention
The present invention relates to a successive approximation register (SAR) analog-to-digital converter (ADC) and, more particularly, to a calibrated SAR ADC that has a reduced size.
2. Description of the Related Art
Current-generation integrated circuits often include both analog and digital circuits. An analog-to-digital converter (ADC) is an electronic circuit that converts an analog signal into a digital word that represents the analog signal so that the analog signal can be processed by a digital circuit. One well-known type of ADC is a successive approximation register (SAR) ADC.
A SAR ADC includes a digital-to-analog converter (DAC), which is commonly implemented with a series of capacitors and a number of switches. The capacitors have top plates that are connected together, and bottom plates that are individually connectable by way of the switches to an input voltage, a reference voltage, and ground.
The capacitors include a number of binary-valued capacitors, such as 1C, 2C, 4C, 8C, and 16C, where 1C represents the capacitance and plate area of the smallest capacitor that can be fabricated with a given process. A 16C capacitor has 16× the capacitance and plate area of the 1C capacitor, while an 8C capacitor has 8× the capacitance and plate area of the 1C capacitor.
The binary-valued capacitors include a 1C dummy capacitor that allows the capacitor values to be evenly divided. For example, the first four binary-valued capacitors (1C, 2C, 4C, 8C) in combination with the 1C dummy capacitor have a total capacitance of 16C, which is equal to the fifth binary-valued capacitor (16C). Similarly, the first three binary-valued capacitors (1C, 2C, 4C) in combination with the 1C dummy capacitor have a total capacitance of 8C, which is equal to the fourth binary-valued capacitor (8C).
Each of the binary-valued capacitors, with the exception of the dummy capacitor, corresponds to a bit in the digital word output by the SAR ADC. For example, a SAR ADC that outputs a five-bit word typically has six binary-valued capacitors, five bit capacitors and one dummy capacitor.
The largest binary-valued capacitor (16C in the present example) represents the most significant bit (MSB), while the smallest binary-valued capacitor (1C in the present example) represents the least significant bit (LSB). In addition to the capacitive-based DAC, a SAR ADC also includes a comparator and a controller.
In operation, the capacitive-based DAC receives a sequence of control words from the controller, which controls the positions of the switches which, in turn, determine whether the input voltage, the reference voltage, or ground is connected to the binary-weighted capacitors.
The sequence of connecting and reconnecting the voltages generates a sequence of DAC voltages at the input of the comparator, which compares the sequence of DAC voltages to ground, and outputs a sequence of logic values that represents the results of the comparisons. The controller interprets the sequence of logic values, and sequentially assigns a logic state to each bit position in the digital word that represents the input voltage.
A high-resolution SAR ADC can be formed by increasing the number of bits within the digital word that represents the input voltage. For example, a SAR ADC that outputs a 10-bit word has a much higher resolution than a SAR ADC that outputs a 5-bit word. However, as the number of bits increase, the size of the largest binary-valued capacitor significantly increases. The largest capacitor in a 5-bit word is 16× larger than the smallest capacitor, whereas the largest capacitor in a 10-bit word is 1024× larger.
One approach to reducing the size of a high-resolution SAR ADC is to use a segmented capacitor-based DAC. In the smallest segmented capacitor-based DAC, a first group of capacitors and switches are used to form a main DAC, while a second group of capacitors and switches are used to form a sub DAC that is connected to the main DAC by an attenuating capacitor.
For example, the main DAC can include a number of binary-valued capacitors, such as 1C, 2C, 4C, 8C, and 16C, while the sub DAC can include a number of binary-valued capacitors, such as 1C, 2C, and 4C. The attenuating capacitor reduces the effect of the capacitors in the sub DAC so that the 4C capacitor in the sub DAC has the effect of a 1/2C capacitor, the 2C capacitor in the sub DAC has the effect of the 1/4C capacitor, and the 1C capacitor in the sub DAC has the effect of the 1/8C capacitor. Thus, in the present example, an 8-bit DAC formed with a main DAC and a sub DAC can be formed in a much smaller area than an 8-bit DAC that is formed with 1C, 2C, 4C, 8C, 16C, 32C, 64C, and 128C.